1. Field of the Invention
This invention relates to a process for formation of a self-aligned pocket in the fabrication of MOS devices and the MOS devices.
2. Brief Description of the Prior Art
A development in the fabrication of MOS semiconductor devices has included the pocket process. The pocket process is a process whereby a region of dopants opposite to the type used for source/drain (and/or drain extension) regions is formed adjacent to the source/drain (and/or drain extension regions), referred to herein as a "pocket region". The lateral extent of the pocket region is less than the channel length of the MOSFET such that the formation of the pocket results in a laterally non-uniform dopant region from the source and/or drain and/or drain extension to the interior of the channel region. The pocket regions are typically formed by implantation over an entire moat (or active area) region such that for MOSFETs with shallow junction depth, a large junction capacitance (Cj) can arise from the pocket process. The benefits of this dopant profile are reduced short-channel effects (i.e., reduced threshold-voltage rolloff) and reduced variation of drive current with variation in gate length.
For shallow junction CMOS, the pocket dopants may also extend to a vertical depth greater than the drain extension region (and/or shallow source/drain region), thus creating a high bottomwall capacitance between the pocket region and a shallow source/drain region. While a deeper source/drain region to a depth greater than the pocket region can be formed to reduce the bottomwall capacitance, such a deep source/drain junction is not scalable to ultra-high-density MOSFET technology since such a deep source/drain junction would result in undesirable short-channel effects as the spacer separation of the gate electrode to the edge of the deep source/drain region is decreased in ultra-high-density MOSFET technology.
An example of such a prior art device is shown in FIGS. 1a and 1b wherein there is shown a semiconductor substrate 1, for example doped p-type, having a gate electrode 3 spaced from the substrate by a dielectric layer 5. Shallow doped extension regions 7 (denoted herein as drain extension regions and, for example, doped n-type) may be formed on each side of the gate electrode 3 with or without sidewall dielectric spacers 12 (sidewall spacers 12 shown in FIG. 1b) provided adjacent to the gate electrode 3 prior to formation of the doped extension regions 7. Pocket regions 9 of doping type opposite (e.g., p-type) to that of the drain extension regions 7 may be formed by means of implantation prior to or after formation of the drain extension regions 7. Typically, the pocket region 9 extends beyond the drain extension regions 7 in both the lateral and vertical directions, whereby a large bottomwall capacitance can result due to the n/p junction region formed at the bottom of the drain extension region due to the overlap with the pocket region 9 over the entire active area. The doping in the pocket region 9 from the pocket process may be of higher concentration than the doping of the substrate 1.
To reduce this bottomwall capacitance over the entire active area, a deeper source/drain region 10 (in this example, n-type) can be formed after formation of sidewall spacers 12 so that the bottomwall overlap of the deeper source/drain region 10 and the pocket regions 9 is eliminated, thus reducing the bottomwall capacitance in these regions as shown in FIG. 1b. Nonetheless, the bottomwall capacitance arising from the overlap of the remaining length of the drain extension region 7 and the underlying pocket doping 9 still remains. As noted above, while a deeper source/drain region 10 to a depth greater than the pocket region 9 can be formed to reduce the bottomwall capacitance, a further problem exists in that such a deep source/drain junction is not scalable to ultra-high-density MOSFET technology wherein such a deep source/drain junction would result in undesirable short-channel effects as the spacer separation of the gate electrode 3 to the edge of the deep source/drain region is decreased in ultra-high-density MOSFET technology.
In addition, a doped diffusion source has been known and used in the prior art for the purpose of forming the shallow drain extension regions 7 having a conductivity type the same as the deep source-drain regions 10.
It is desired that there be provided a self-aligned pocket doping process with low junction capacitance, Cj, and without the need for the deeper source/drain region to achieve the low Cj (bottomwall) in the active region.